libera/#maemo-leste/ Friday, 2021-11-12

mighty17[m]freemangordon: i think i know why phosh doesnt work14:18
mighty17[m]`failed to load driver: omapdrm` even with `export MESA_LOADER_DRIVER_OVERRIDE=pvr` , so somehow its hardcoded to use omapdrm?14:18
mighty17[m]i uh dont understand what is going on, i copied omapdrm_dri.so to become pvr_dri.so and that works with kmscube with `export MESA_LOADER_DRIVER_OVERRIDE=pvr`14:21
mighty17[m]but if i do `export MESA_LOADER_DRIVER_OVERRIDE=omapdrm` that does not work14:21
mighty17[m]yup def an issue with it not using pvr_dri.so but instead wanting omapdrm15:01
uvosits using the wrong render node probubly15:03
uvosdosent phosh use wlroots?15:03
uvosie are you using patched wlroots15:03
uvosalso check if its not static linking15:04
mighty17[m]phosh does use wlroots (and phoc)15:08
mighty17[m]uvos: yes, as it works with chromeos mesa anyways15:08
mighty17[m]uvos: with ls -al?15:09
uvos?15:10
uvosif it dosent use wlroots its irellivant if it uses static linking for something else15:10
uvosoh i read that wrong15:11
uvosyeah check if it links to it dinamicly with ldd15:12
mighty17[m]<uvos> "also check if its not static..." <- i cant seem to find anything about it on phoc/wlroots source code15:12
uvosjust ldd the wm15:12
uvosbut that would not explain why it works with chomeos mesa anyhow.15:13
uvosother stuff dose work right?15:13
mighty17[m]static linking with omapdrm in source code?15:13
uvosno static linking wlroots therfore using some unpatched version15:14
mighty17[m]it does use wlroots15:14
uvosldd /usr/bin/phoc or whatever will tell you15:14
mighty17[m]other stuff like kmscube, glmark2-es2-drm does work15:19
mighty17[m]and so does weston15:19
uvoswhat about something else using wlroots15:19
uvoseg sway15:19
mighty17[m]<uvos> "ldd /usr/bin/phoc or whatever..." <- https://paste.debian.net/1219289/15:21
mighty17[m]weston does use wlroots doesnt it?15:22
uvosno15:22
uvosso it loads libwlroots.so.7 => /usr/lib/libwlroots.so.715:23
uvosdid you patch libwlroots?15:23
mighty17[m]anyways for sway i'll need to patch another version of wlroots (0.14) instead of 0.12 that phosh uses15:25
mighty17[m]uvos: https://gitlab.com/antoni.aloytorrens/p-wlroots/-/tree/master/apkbuild15:25
mighty17[m]`MESA-LOADER: failed to open omapdrm: Error loading shared library /usr/lib/xorg/modules/dri/omapdrm_dri.so: No such file or directory (search paths /usr/lib/xorg/modules/dri, suffix _dri)` uhm whaat?!15:42
mighty17[m]so its hardcoded somewhere to only use omapdrm and not pvr?15:42
uvosno pvr is failing for some reason so it trys to load omapdrm15:54
uvosprobubly15:54
uvosmaybe checkout the section where mesa decides what module to use with gdb15:54
mighty17[m]ah figured it out!15:58
mighty17[m]my starter session was being annoying15:58
mighty17[m]well phosh works now 🎉16:01
freemangordonmighty17[m]: hmm? it works with HW accelleration?18:00
freemangordonOTOH, seems sgx driver has issues with TILER memory18:00
freemangordonor, it is omapdrm driver that maps wrong addresses18:01
freemangordontmlind: ^^^18:01
mighty17[m]freemangordon: Yess!!!18:02
freemangordongood :)18:02
mighty17[m]And no more crashes!! It's really amazing18:03
tmlindfreemangordon: not following you, care to clarify on the wrong address part?18:11
freemangordonwhen I do xrandr rotate and use PVR for accelerated 2d, TILER allocated BOs are wrongly accessed18:15
freemangordonseems like either omapdrm provides wrong dma address to pvr driver or pvr driver gets wrong address mapping for this dma address18:16
freemangordonI guess PVR ends up in   omap_gem_pin() when it needs DMA address, right?18:17
freemangordontmlind: SGX should see TILER addresses, correct?18:21
tmlindno idea how that is supposed to work18:22
tmlindhave you looked at the /sys/kernel/debug tiler output?18:22
tmlindthat might provide some more info18:22
freemangordonsec18:23
freemangordonwill do now18:23
freemangordonanything in particular to look for?18:28
freemangordonit seems there is tiler buffer at address 0x7010000018:29
dreamerman, we should get zmatt into here. he dived into TILER heavily some time ago18:29
freemangordonplease ask him to join18:29
dreamer/invite zmatt18:29
dreamerI poked him in another channel :)18:32
freemangordonthanks18:32
tmlindfreemangordon: i recall seeing some memory leak cases under the tiler debugfs entry after several rotations with ddk-1.918:33
dreamerbecause the Pyra uses a phone screen they also needed to do some tiler tricks to get proper fb rotation going18:34
dreamerhttps://en.wikipedia.org/wiki/DragonBox_Pyra18:34
dreamerbtw he also noticed recent merges over @ TI SGX branches. however couple SoCs where left out which seemed odd18:34
dreamerI lost the link to that18:35
freemangordontmlind: I don;t think we have memleak, seems like another issue to me18:35
tmlindok, the memory leak was clearly visible with stuff never getting freed in the debug output for tiler18:36
freemangordonit seems like sgx accesses the backing memory addresses, not the tiler addresses]18:36
freemangordonor, the address it gets (how?) is wrong18:37
tmlindheh the "how" part again :)18:37
freemangordonwell, what I think happens is:18:37
freemangordonthere is   PVRSRVMapFullDmaBuf() function in the blobs, which gets BO fd as one of the parameters18:38
freemangordonso I think PVR driver imports this BO, (using some kernel gem_import() or whatever function) into its mmu18:39
freemangordonhowever, my theory is that this gem_import provides wrong address to SGX driver for TILED BOs18:39
dreamerPyra is on omap5 so maybe not applicable. only thing I can find currently is: https://www.pyra-handheld.com/wiki/index.php?title=Display#Tiler18:41
dreamerso yeah, need to get him in here. hope he reads the highlight I gave him :#18:42
tmlindfreemangordon: hmms so why would 3d stuff work then and 2d not? tiler is being used the same way, no?18:44
freemangordonTILER is not used for 3d stuff18:45
freemangordonto allocate TILER BO one needs to call omap_bo_new_tiled()18:45
freemangordonand this is done only by omap-video driver for scanout buffers18:46
tmlindok18:46
tmlindhmm but it sort of worked with ddk-1.9 and the same kernel tiler code more or less?18:47
freemangordonI guess it was not using PVR for accelerated 2D18:47
freemangordonyou you work with mmap-ed memory only, tehre is no issue18:47
freemangordon*if you18:47
tmlindok18:48
tmlindcould it be some dma address issue where the rotated bit is left out of the address? if something is cast to 32-bit dma address for the tiler?18:50
tmlindsee the tiler rotated view addresses int trm at "Table 2-1. Global Memory Space Mapping"18:51
tmlindhmm i guess it would then just not rotate though18:51
tmlindfreemangordon: also not that for ddk-1.9 we had the legacy omapdrm ioctl stuff patched back in18:54
tmlindwe should not need those ioctl hacks though hopefully at all18:55
* tmlind detaching from computer19:02
freemangordonsorry, phone call19:03
uvosi gues dumping the sgx's mmu table and checking if it has the tiler space mapped is not an option19:05
uvossince no documentation19:05
freemangordonactually driver dumps the table19:07
freemangordonlemme see if I will be able to understand something19:12
freemangordonhmm, looks ok19:14
freemangordonhttps://pastebin.com/vji9Gbiv19:14
freemangordonif 70100000 is correctly calculated address19:15
uvoswell thats the question, no idea :P19:20
freemangordon70000000 it the base address for 32 bit container19:21
freemangordonnot sure 100000 is 90 deg rotation view though19:23
freemangordonoh, but ofc19:23
freemangordonmost-probably this is non-rotated TILER view19:24
freemangordonlike, base address19:24
freemangordonhmmm19:24
freemangordonhow is PVR driver supposed to know what offset to add to this?19:24
freemangordonto get rotated view that is19:25
freemangordonuvos: tmlind: this https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/omapdrm/omap_gem.c#L89019:26
uvosit might just be broken - since ti themselves dont use pvr for 2d for anything since ddk1.14 and more modern omaps (-60 and omap5) have a dedicated 2d engine. one of the ddk1.9 ioctls might have been this.19:27
uvosah19:27
freemangordonso, omap_gem_rotated_dma_addr() is called only by the framebuffer code19:27
freemangordonbased on the rotation that is set to the framebuffer19:28
uvosah wait19:28
uvoswhy would sgx want to use the 90deg view? should it not be using 0deg and dss use 90deg view?19:29
uvosor is it the other way around?19:29
freemangordonthat's one of the questions I dont; have answers to19:29
freemangordonor, maybe for tiler bos I shall transpose?19:30
freemangordonlemem try19:30
freemangordon*lemme19:30
freemangordonuvos: I think it shall see rotated TILER address, how it is supposed to draw a line (rotated) if not.19:49
uvosfreemangordon: you draw a line using the non rotated view and the rotated view is then scanned out?19:50
uvosfreemangordon: how else is it supposed to work?19:50
freemangordonhmm19:50
uvosfreemangordon: if you draw a line into the rotated view and also scann it out you get no change no?19:50
freemangordonbut then why I see it draw mostly out of screen19:50
freemangordonlemme take a picture to show what I mean19:51
uvosthe buffer your allocating is the wrong size maybe?19:53
freemangordonnot, it is fine19:54
freemangordonif you acces it through mmap it is ok19:54
freemangordononly pvr2d sees it wrong19:54
freemangordonok, seems we have negative offset on y19:55
uvosthe header pvr gets might be wrong? sees a 540x960 buffer in landscape?19:55
uvosi gues the line would be more than ofset then (it would be spread all over the place)19:55
uvosnegavtive y in what space? native display or rotated buffer?19:57
freemangordonI see only top (maybe) 256 pixels painted in the fill color19:58
uvostop being the top in native orientaion?19:58
freemangordonno, top in rotated orientation19:59
uvosok that excludes the possible pvr thinks its drawing into a 540x960 buffer20:00
uvos*possibility20:00
freemangordonyeah20:00
uvosno idea then, fun :)20:01
freemangordonif I hardcode X size, it is ok, like if I hardcode 512, I have 512x? blue rectangle20:02
freemangordonbut I cannot extend on vertical20:02
freemangordonso it seems to try to draw correct thing20:02
freemangordonhmm, maybe this is 64 lines20:02
calebtheythem[m]heyo, my Photon Q arrived, it's in amazing condition, super chuffed. Anyway it looks like it exposes UART in the same way as the droid 4, the Android kernel has some sysfs bits you can poke to put the mux into UART mode manually, but I wasn't able to get it to spit out any data, any ideas?20:14
calebtheythem[m]I did manage to find some info about the Moto X which uses almost the same SoC and released soon after the Photon Q, it isn't a slider phone unfortunately. But I found out that it exposes UART on the unpopulated JTAG header, I would guess the Photon Q uses the same pinout there. So I should be able to get UART that way20:16
uvoson the d4 the android kernel never dose anything with the uart (iirc its not even configured in dts)20:16
uvosso you have to kexec somewhere else if you want to use it20:17
uvoslike los maybe20:17
dreamerfreemangordon: ^20:17
zmattI was summoned?20:17
dreamer:)20:17
dreamerfreemangordon: can you summarize the tiler issue for zmatt? :)20:18
freemangordonzmatt: hi!20:18
zmattare we talking omap4 or omap5 btw?20:19
freemangordonwell, I am having hard time trying to correctly accelerate 2d operations by using PVR @D ops on TILER buffers20:19
freemangordonomap420:19
freemangordonbut should be the same, no?20:19
freemangordonbeside cache flags, IIUC20:20
zmattthey're *mostly* the same yes... iirc main difference is that omap5 tiler has separate pagetables for 2d and 1d20:20
freemangordonthe same is for omap4, IIUC20:20
freemangordonDMM vs TILER 2d20:20
freemangordonbut, I don;t think it makes any difference in the particular scenario20:21
freemangordonso, basically20:21
freemangordonI am implementing xorg EXA that is supposed to accelerate 2D ops by using SGX20:21
freemangordonin 'native' view it is fine20:22
freemangordonBTW, so far I have implemented basic SolidFill only20:22
freemangordonbut as POC it should be ok20:22
zmattright, since omap4 didn't have the separate 2d gpu20:22
freemangordonhowever, as soon as a TILER bo is allocated (for rotated view), only the upper (maybe) 64 lines are filled20:23
freemangordonwith the fill color that is20:23
uvoszmatt: except -60 :P20:23
freemangordonlook at https://pastebin.com/vji9Gbiv20:23
uvos\me pedantic20:23
* uvos pedantic20:23
calebtheythem[m]I'm running LOS 14.1 now (i previously tried in TWRP), from what i've seen /dev/ttyHSL0 is the right UART, but nothing20:23
calebtheythem[m]Someone else suggested it might be that the wires I'm using are too long and the signal is getting lost, is that something the droid 4 suffers with?20:23
freemangordonzmatt: to me SGX MMU seems to be correctly setup20:24
zmattuvos: 4470 you mean20:24
uvoscalebtheythem[m]: not really20:24
freemangordonDMA address of the buffer looks fine to me, to the extend I understand how all this is supposed to work20:24
zmattfreemangordon: how many bits/pixel ?20:24
freemangordonunfortunately the extend is not as wide as I would like it to be :D20:25
freemangordon32bpp20:25
freemangordon960x54420:25
freemangordonmotorola droid4 that is20:25
freemangordonnative orientation is portrait20:25
uvoszmatt: right -7020:26
freemangordonI am using  PVR2DBlt for drawing20:26
freemangordonif that makes any difference20:26
freemangordonzmatt: so, SGX core should see *unrotated* DMA address, right?20:27
uvoscalebtheythem[m]: very unlikely, but check with a scope/la if you have one20:27
freemangordonBTW, the same BO, when accessed by userspace (mmap-ed) is ok20:28
calebtheythem[m]uvos: I'll take a look with a multimeter, I'm just worried to go chasing hardware issues if it turns out the UART port is just disabled lol20:28
uvoscalebtheythem[m]: where do you get the idea that the uart is multiplexed to the usb port btw?20:29
calebtheythem[m]I did some initial mainline porting here - https://github.com/calebccff/linux/commits/asanti-bringup, device just sits on the bootloader splash screen though, probably figuring out how UART works on the downstream kernel is the best place to start20:29
zmattfreemangordon: the orientation seen by masters other than DSS and IVA-HD is configurable per master, but afaik linux always leaves those in normal orientation and just asks DSS to scan the buffer out in whatever orientation is needed20:29
freemangordonmhm20:29
freemangordonmy understanding as well20:29
uvosthat also makes the most sense20:29
freemangordonbut that, why it provides DMA address in TILER address space and not in DMM?20:30
freemangordon*but then20:30
calebtheythem[m]uvos: this driver is built on downstream and shows up in logs https://github.com/MotorolaMobilityLLC/kernel-msm/blob/kitkat-mr1-rel-razrm/drivers/mfd/emu-det.c20:30
freemangordonomapdrm that is20:30
zmattI don't know what you mean by that... linux uses the words tiler and dmm in a way that doesn't actually match hardware meaning20:30
freemangordonrotated BOs are allocated in TILER 2d20:31
uvosyou have to draw into tiler space for caching purposes maybe?20:31
zmattrotatable BOs would be a better term20:31
freemangordonok, will use that20:31
zmattyou have to draw into tiler space20:31
freemangordonuvos: yeah, maube20:31
freemangordon*maybe20:31
freemangordonzmatt: ok20:31
zmattthe underlying ram has the pixels totally jumbled up20:32
freemangordonhmm, wait, why so?20:32
zmattbecause tiler turns 2d spatial locality into 1d spatial locality20:32
uvoscalebtheythem[m]: ok20:32
freemangordonok20:32
freemangordonanyway, this is detail that I don't think matters for the issue20:33
zmattso like, each 32x32 block of pixels is one page of underlying ram (... sort of, ignoring interleaving)20:33
freemangordonok, so, do you think SGX MMU is correctly set up? https://pastebin.com/vji9Gbiv20:34
uvoscalebtheythem[m]: i dont think we can help your really the xt897's hardware is totaly different from xt860/xt875/xt89420:34
uvoscalebtheythem[m]: besides me having one i dont think anyone here has had any interaction with one20:35
freemangordon0x70000000 is the start of 32 bpp TILER space, IIUC20:35
freemangordonbut then, why 0x100000 offset? this is "native" view or what?20:35
uvoslike the uart behavior/multiplexing on xt894  is controled by its custom motorola pmic20:36
calebtheythem[m]uvos: yeah i suspected as much, thanks anyway. Hopefully I'll be able to track down UART on the JTAG header and go from there.20:36
uvoswhich you dont have20:36
uvosyeah :)20:36
calebtheythem[m]oh interesting20:36
freemangordonhmm, wait, what is the stride of rotatable BOs?20:39
freemangordon4096?20:39
zmattfreemangordon: https://pastebin.com/raw/n7zUGyxS20:39
zmattthat's how addresses in tiler virtual space are decoded20:39
freemangordonsi, it is row 16 in 32bit space, IIUC20:42
freemangordon*sp20:42
freemangordonaah20:42
freemangordonso20:42
freemangordonnot that I understand what is this supposed to mean20:42
zmattmore detailed: https://pastebin.com/raw/H1hATHRU20:43
zmattthe ypage and xpage parts are combined to select a page20:43
freemangordonso, this is not linear?20:44
zmattno, that's what I said: each 32x32-pixel block (for 32-bit mode) is a single 4K page20:44
zmatt64x32-pixel for 16-bit mode, 64x64-pixel for 8-bit mode20:45
freemangordonI mean 'linear' in terms of addressing20:45
zmattI'm not sure what you mean by that... the tiler virtual space is a single giant big rectangle of pixels from which you carve your buffers20:46
freemangordonI mean in terms of SGX MMU20:46
freemangordonlemme do some calculations20:46
zmattbuffers are not contiguous, unless you're actually using the entire width (8192 pixels in 32-bit mode)20:47
freemangordonso, stride is 8192?20:47
freemangordonoh, 8192*420:47
freemangordonis that correct?20:48
zmatt8Kpixels, 32KB yes20:48
zmatt(32KB in 16- and 32-bit mode, 16KB in 8-bit mode)20:48
freemangordonah, so maybe thats why it draws on only a small part of the screen20:48
freemangordonhmm, who is supposed to provide the correct stride to sgx driver?20:49
freemangordonbasically it imports gem bufefr20:49
zmatt¯\_(ツ)_/¯20:49
zmattyou probably want to hide the real stride anyway20:50
zmattsimilar to how it's hidden from userspace20:50
zmattusing the mmu20:50
freemangordonwhich mmu? SGX one?20:50
zmatt(but that's only really possible if buffers are page-aligned in tiler space)20:50
zmattthe sgx one for sgx, the arm one for userspace20:50
zmattthough mainline linux does a gross and really inefficient hack for userspace20:51
freemangordonMMU_Alloc: uSize=0x1fe000, flags=0x0, align=0x100020:51
freemangordonI guess the align here is incorrect20:51
zmattto avoid having to properly align the buffers themselves20:51
zmattfor the pyra kernel I just hacked in proper alignment, at the cost of wasting some tiler virtual space (but that's less a problem on omap5 than omap4)20:52
freemangordonbut, how do you setup SGX MMU then?20:52
freemangordonI mean - obviously ATM it uses wrong stride20:53
zmattnever got to that point20:53
freemangordonno 3d acceleration for rotated BOs?20:54
zmattin fullscreen mode it's more efficient to let sgx do the rotation anyway20:54
freemangordonSGX like glamor?20:54
freemangordonor rather - like GL (rotate through shader)?20:55
zmatt(the ideal solution is to have the sgx wsegl layer report the orientation to the driver which then transparently performs the rotation for you, which is how it's done on android)20:55
freemangordonwhich driver? kernel mode?20:55
zmattno the userspace libs20:55
zmattthe API to the (window-)system glue layer includes the ability for that glue layer to report back the desired orientation20:56
freemangordonbut how do they rotate? I mean - who is the one that performs the real rotation? 3D core?20:56
uvoswsegl dosent exist in ddk1.1720:56
uvosit was droped with 1.14 no20:56
uvos?20:56
freemangordonthat doesn;t really matter20:56
zmattfreemangordon: that's an internal detail but presumably it just applies a rotation to the coordinate system20:56
zmattuvos: uhh what?20:56
freemangordonmost of the functions are still there (for 2D and 3D blits)20:57
freemangordonzmatt: yeah, no longer WSXXX_EGL.so libs20:57
freemangordoneverything is done through dma_buf/DRI in 1.1720:58
freemangordonzmatt: it could be a detail, but an important one. on OMAP5 you might not care about the performance, but we aim omap3 here :p20:58
zmatt"might not care about the performance" ? what?20:59
freemangordonI mean - omap5 has 2d core, afaik20:59
zmattright sgx isn't used for 2d there20:59
freemangordonalso, it is times more powerful than omap3, so even if you rotate in SW, FPS will drop by 2-321:00
uvosbut the rotation is perfomed on 3d engine21:00
uvosif it "works like on android"21:00
freemangordonthat's what I am asking :)21:00
freemangordonuvos: 3d engine like shader?21:00
uvosno idea how its implemened but on los the tiler data debug data dosent change with rotation. on android the exact implementation is in the propriatary hwcomposer plugin.21:02
zmattuvos: I was describing how sgx can be asked to do the rotation itself instead (for fullscreen 3d) of using a rotated fb, but that would require a custom wsegl layer21:02
zmattI'm not sure what solution has been used, I've been out of the loop for a while now21:02
uvoszmatt: sure but how do you rotate the output of the 2d core?21:03
freemangordonso, to sum it up - it seems SGX MMU is not set-up to access the whole rotated BO, given that stride in native orientation for the particular BO is 32 KiB21:03
zmattuvos: sgx isn't used for 2d21:03
zmatton omap521:03
uvosright thats what i mean21:03
freemangordonzmatt: whatever is used, how do you rotate it?21:03
uvoson pyra you draw x elements with the sperate 2d core21:04
uvoshow do you rotrate that?21:04
uvosupload it to sgx as a texure and transform it?21:04
uvosor what21:04
zmattfreemangordon: if you did a blit instead of a fill you probably would have noticed the issue of the wrong stride ;)21:04
zmattfreemangordon: (rotation of 3d) 21:02 < zmatt> I'm not sure what solution has been used, I've been out of the loop for a while now21:05
freemangordonzmatt: yeah, but it is more complicated to implement, that's why I started with simple fills21:05
zmattheh, btw this is what you get when you bypass TILER when drawing an image: https://liktaanjeneus.nl/very-tiled-fbdev.jpg21:06
zmatt(but then display it using TILER)21:06
uvospretty21:06
freemangordonnice :)21:06
zmattiirc because I used write() on the fbdev and this turned out to works incorrectly for tiled buffers21:07
* freemangordon checkes how SGX driver imports omap_bo BOs21:07
zmattfirst question would be, how are they exported?21:07
zmattiirc even that was broken21:07
freemangordonthey are exported as FDs21:08
zmattthat's not what I meant21:08
freemangordonbut what?21:08
freemangordonprovided DMA address seems correct to me21:08
zmattthe tiled buffer is non-contiguous and possibly not even page-aligned, is its scatterlist correct?21:08
freemangordonshould be21:09
freemangordonwhy you said it is non-contiguous?21:09
freemangordonthe backing RAM is not, but it's addressed through DMM, IIUC21:09
zmattbecause its stride is much larger than its width, and that space belongs to other buffers21:09
freemangordonah21:10
freemangordonoh21:10
freemangordonomg21:10
freemangordonI see what you mean21:10
buZzhi zmatt \o/21:10
freemangordonhmm....21:10
freemangordonso, a 'row' is not assigned to a single BO?21:11
freemangordonok, seems SGX expects contiguous memory21:11
zmattfreemangordon: I know this is something I was working on at some point, but I don't really remember any details about it: https://github.com/mvduin/linux/commit/78b2f59352a2697590a7b9ed8ffed1ad7f98b98d21:11
freemangordonand most-probably that's our issue21:11
zmattfreemangordon: a row is indeed not a single BO21:12
freemangordonok, this explains it21:12
freemangordonat least partially21:12
zmattbut if the buffer is forced to be page-aligned (start address and width in bytes) then you can make it *appear* contiguous using the mmu, that's what I said earlier21:13
zmattthen the stride will seem to be the width rounded up to a multiple of 4KB, same as in userspace21:13
zmatt(or rather, the actual width *will be* the requested width rounded up to a multiple of 4KB)21:13
zmatteach line is then an integral number of pages, so the scatterlist can deal with that and the importer doesn't need to know the details21:14
freemangordonhmm, I guess I shall ask Tomi about that21:15
freemangordonwhat about allocating the full row for a line?21:15
zmatt(and the stride perceived by sgx is then the same as the stride perceived by userspace)21:15
zmattthat would be even more wasteful without any benefit21:15
freemangordonwe will waste TILER space, but so what21:15
uvostiler space is 128mb21:16
zmattand it would make the stride different for sgx and for userspace, which sounds like it'll bite you in the ass21:16
uvosand on android the video decoding uses lots of it21:16
freemangordonyeah, right21:16
freemangordonbut, userspace stride I see is 409621:16
zmattwidth rounded up to multiple of 4KB21:16
freemangordonso something lies SGX driver about the size of th buffer21:16
freemangordonsize=0x1fe00021:17
zmattbtw forcing page alignment is like a single-line change, or at least it was in 4.19: https://github.com/mvduin/linux/commit/6629b3a97bf30fd59c4eb941087a3fca1ac4847121:17
freemangordon0x1fe000 = 960x544x421:18
zmattso yeah, that WiP patch ( https://github.com/mvduin/linux/commit/78b2f59352a2697590a7b9ed8ffed1ad7f98b98d ) looks like for 2d buffers I create a scatterlist with one entry per line of the buffer21:20
freemangordonBTW, we'll have the same issue for VRFB on omap321:21
zmattwhen combined with forcing page-alignment of buffer, it'll mean that if the importer uses the MMU to make the scatterlist seem contiguous, the result is a contiguous buffer with a stride equal to width rounded up to a multiple of 4KB, same as linux userspace21:21
freemangordonmhm21:22
freemangordonI have to verify how is BO imported by SGX driver21:23
zmattyeah, I don't remember if this patch was tested *at all* yet21:23
freemangordonbecause all I see is that it receives only TILED address and a size21:24
freemangordon*TILER21:24
zmattso it's not using dma_buf ?21:25
freemangordonno idea what it does :)21:25
zmattor does it just fail if given a scatterlist with more than one element?21:25
freemangordonhave to check21:25
freemangordonI have a blob function called   PVRSRVMapFullDmaBuf()21:26
zmattthat sounds like it would need to be fixed anyway, dma buffers do not generally come with a promise of being contiguous21:26
freemangordonyeah21:26
freemangordonalso, I was not able to find a way to allocate TILER GDB BO21:27
freemangordon*GBM21:27
freemangordonzmatt: ok, thanks for the help, I think I now have a better understanding on what is going on21:29
zmattI also force page-alignment of buffers to allow for fast userspace mapping: https://github.com/mvduin/linux/commit/a8612b1ca3e69afa551b8d9605b72c5acbeb859e21:29
zmattsince the mainline mechanism is excruciatingly slow21:30
freemangordonwhy not send those for upstreaming?21:30
zmattbecause these are hacky patches that basically undo trade-offs mainline chose deliberatley21:31
zmatt*deliberately21:31
zmattmainline's hack conserves tiler virtual memory space21:31
freemangordonI see21:32
zmattthat had to do with iva-hd iirc21:33
zmattand omap4 also uses tiler/dmm as a general iommu to make non-contiguous buffers appear contiguous, and on omap4 that uses the same virtual memory space21:34
freemangordonyeah21:34
zmattwhich is really awkaward since it caves out awkward non-rectangular chunks of the tiler space21:34
zmattpotentially at least, depends a bit on where it allocates21:35
zmatton omap5 there's a separate page table used for page mode21:36
zmattto avoid that problem21:36
zmattso the patches I did were to maximize performance with little care about wasting tiler virtual space21:37
freemangordonok, I will have to teach SGX driver to correctly set its MMU for such buffers21:38
zmattit shouldn't require anything tiler-specific though, just support for non-contiguous dmabufs21:38
zmattwhich shouldn't be a problem since it has an MMU to make these appear contiguous to the SGX core21:39
zmattthose kernel messages you pastbinned earlier showed "MMU_MapScatter" which sounds to me like the functionality is there already in the MMU code at least?21:40
freemangordonyeah, will have to look into it21:44
freemangordon"Create a linear mapping for a range of pages at a specified"21:45
freemangordonnot really what we need :)21:46
zmattso why is there "Scatter" in its name then? :P21:46
freemangordonno idea21:46
freemangordonbut there is   MMU_MapPages with exactly the same comment :)21:47
zmattoh wait, *list* of pages21:48
zmattthat's scatter indeed21:48
freemangordonwhere do you see *list*?21:48
zmattin the mmu.h header21:48
freemangordonI see *range*21:48
freemangordonhmm21:48
freemangordonmaybe they copied wrong comment in mmu.c21:49
zmatthttps://git.ti.com/cgit/graphics/omap5-sgx-ddk-linux/tree/eurasia_km/services4/srvkm/devices/sgx/mmu.h?h=ti-img-sgx/1.17.4948957/k4.19#n31221:50
freemangordonsame here, but see the comment in mmu.c21:50
zmattyeah, copy-paste error21:51
freemangordonmhm21:51
freemangordonok, lemme see how that worls21:51
freemangordonyeah, this will map pages21:52
freemangordonlike list of pages21:53
freemangordonhmm, seems SGX driver does its job through dma_buf API22:15
freemangordonso, it calls   dma_buf_map_attachment() and gets scatterlist22:17
freemangordonso, it seems this list is incorrect22:17
zmattwhich makes sense, it was broken when I last worked on it and TILER probably hasn't gotten much love and attention since then22:34
freemangordonok, lemme see if I get that correctly22:37
freemangordonit seems omap_gem_map_dma_buf creates scatterlist for a single contiguous memory block22:39
freemangordonwhich is absolutely wrong22:39
zmattyep22:40
freemangordonI see now what happesnt22:40
freemangordonso, I have to create a correct scatterlist there and all will start working correctly22:40
zmattthat's what I was working on fixing in https://github.com/mvduin/linux/commit/78b2f59352a2697590a7b9ed8ffed1ad7f98b98d22:40
zmatt(I don't remember how far I got, it could be anywhere from "doesn't even compile" to "works perfectly")22:41
freemangordon:D22:41
freemangordonwas about to ask - does it works22:41
freemangordon*work22:41
freemangordondo you remember why this change? https://github.com/mvduin/linux/commit/78b2f59352a2697590a7b9ed8ffed1ad7f98b98d#diff-9b3c6ba4dcbd05c07bafe254dd7bc5fd1ac42fede2f7d43aa8250a20c31eecb3L133922:45
zmattthat's fixed in mainline anyway22:47
zmatthttps://www.lkml.org/lkml/2020/6/18/68722:47
zmattI probably made the same observation while working on this patch22:48
freemangordonnot really https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/omapdrm/omap_gem.c#L129622:50
freemangordonI mean - this is not in mainline22:50
zmattoh huh, weird, this patch series didn't get in?22:50
zmattwell, at least it describes the reason22:51
freemangordonyeah22:52
freemangordonany reason why you didn;t send scaterlist fix for upstreaming?22:52
zmattthis was work in progress and that work got interrupted22:52
freemangordonso you work on that no more?22:53
freemangordonshall I take it from here?22:53
zmattI haven't done anything with this for years22:53
zmatt(I think the relatively recent commit date was because I committed my old uncommitted work in progress for someone else)22:54
freemangordonI see22:54
zmattand indeed feel free to pick it up22:54
freemangordonok, I will pick this up, test it and send a proper patch for upstreaming22:54
zmattit'll need to be rebased first anyway, I see it's committed on top of other hacks/patches22:55
zmattbut that's hopefully not too difficult to unravel22:56
freemangordonI will not cherry-pick, would rather copy/paste. Will see how to give a credit to you when it comes to sending for upstreaming22:56
freemangordonIf you don;t mind22:57
zmattI don't care how it's used or whether/how I'm credited... if it manages to find good use that's already better than it just collecting dust :)22:57
uvosi gues the suggested-by tag is for this case.22:57
freemangordonok22:58
zmattbe sure to sanity-check it, I'm not particularly experienced with kernel development22:58
freemangordonme neither, so I count on the maintainers to verify :)22:59
zmatthehe22:59
freemangordonalso, we have tmlind here on the channel :p23:00
freemangordonok, lets try to quickly hack this code in my tree23:01
zmattit looks like this code is correct even if the BO is not page-aligned, though that obviously can't work with typical importers which want to map entire pages.... so to make this work in practice you'd still need to combine it with forcing page-alignment23:04
freemangordonhmm, why? I mean - in scatterlist you have len and offset for each page?23:04
zmattyes the scatterlist can specify it, and my code does, which is why I said it looks like this code handles that correctly23:05
freemangordonmhm23:05
zmattbut the SGX mmu can only map entire pages, not part of a page23:05
freemangordonlets see23:05
zmatt(or any MMU for that matter)23:05
freemangordonwhat about DMM? can it map partial pages only?23:06
zmattso such buffers are fine if the importer simply uses the scatterlist directly and is trusted to not exceed bounds, but any importer that wants to enforce this using an MMU will need a page-aligned BO23:07
zmattso, obviously DMM works with entire pages, however due to TILER those become 32x32 pixel blocks (in 32-bit mode)23:07
zmattso BOs are 128-byte aligned, not 4096-byte aligned23:08
freemangordonY see23:08
freemangordon*I see23:08
zmattwhich can be fixed by passing PAGE_SIZE as the last argument to tiler_reserve_2d()23:09
zmattinstead of 023:09
freemangordonyeah23:09
freemangordonbut I want to see what will happen iw I just pass correct scatterlist to SGX driver23:09
freemangordon*if23:10
freemangordonbefore changing that23:10
zmattwell there's no possibility (from a hardware point of view) for that to actually work correctly23:10
freemangordonagree, but lets see how wxactly it will fail :)23:11
freemangordonbecause now it does not fail23:11
freemangordonI mean - does not crash23:11
zmattbe sure to try with a buffer whose misalignment makes it touch more pages than it would if it were aligned ;)23:11
freemangordonmost of the times23:11
zmattno but right now it's certainly clobbering random buffers23:12
freemangordonyes23:12
zmatt*hopefully* graphics buffers and not one of the other users of dmm23:12
freemangordonwe don;t have details on SGX MMU23:12
zmattwell in theory the kernel driver source should tell you all you need to know right :)23:13
freemangordonyeah, but SGX driver is not easy to read, you know23:13
freemangordonanyway, lets try to hack some code23:13
zmattit's a bit gauge-eye-out-with-spoon inducing23:13
freemangordonrebooting the device, lets see :)23:28
freemangordonwell, at least display still works :)23:29
freemangordonoopsed on xrand rotation23:30
dsc_are there any QML apps for maemo that work 'well' (in terms of performance)23:45
dsc_maemoleste*23:45

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